Build digital circuits with AND, OR, NOT, NAND, NOR, XOR gates. Wire inputs to outputs and generate truth tables automatically.
Place gates on a canvas, drag wires between their pins, and the simulator computes what the whole circuit does. AND, OR, NOT, NAND, NOR, and XOR each implement one Boolean function, wiring outputs into inputs composes them, and the tool responds with a truth table covering every input combination. The surprise for most users: the table proves functional equivalence, not physical equivalence - identical tables can still behave differently in real hardware, and any circuit whose output feeds back into an input stops being a truth-table circuit at all.
A concrete input and expected output from the current implementation.
Input
Inputs A and B feed an AND gate (output X). X and a third input C feed an OR gate (output Y).
Expected output
A B C | Y 0 0 0 | 0 0 0 1 | 1 0 1 0 | 0 0 1 1 | 1 1 0 0 | 0 1 0 1 | 1 1 1 0 | 1 1 1 1 | 1
X is 1 only when both A and B are 1, and OR outputs 1 whenever either input is 1, so Y is 0 only in the three rows where C is 0 and the AND condition fails: 000, 010, and 100. All eight rows follow from that rule.
Each gate computes a Boolean function of the values arriving on its input wires. AND outputs 1 only when every input is 1; OR outputs 1 when any input is 1; NOT inverts its single input; NAND and NOR are the inverted versions of AND and OR; XOR outputs 1 when exactly one of its two inputs is 1. Connecting a gate output to another gate's input composes these functions into larger expressions.
For a circuit with n independent inputs the tool enumerates 2^n rows covering every combination of 0s and 1s, so each added input doubles the table. Every row is pushed through the network, each gate evaluates its function on the incoming wire values, and one output column appears per circuit output. Three inputs yield 8 rows, four yield 16, and so on.
That is correct behavior. NAND means AND followed by inversion, so its output is 0 in exactly the row where all inputs are 1, and 1 in every other row. If you expected a 1 there, you want the AND gate, or a NOT gate placed after the NAND.
Not in a way you can trust. Latches hold state by feeding an output back into an input, and a truth table only describes combinational circuits, where output is a fixed function of the current inputs. Expect feedback to produce an unstable or meaningless table; use a simulator with clock and timing support for sequential logic.
The example and behavioral notes were checked against the browser implementation. Standards and primary references below define the relevant format, formula, or platform behavior.
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